1. Field of the Invention
Embodiments of the present invention relate to a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device.
2. Description of the Related Art
Wide bandgap semiconductors (semiconductors having a wider bandgap than a silicon (Si) semiconductor) such as silicon carbide (SiC) and gallium nitride (GaN), diamond and the like have favorable properties including a higher critical field strength and a higher thermal conductivity than a silicon semiconductor and thus, application of wide bandgap semiconductors is particularly expected in power devices. Among these semiconductors, silicon carbide semiconductors enable the ON resistance, which is inversely proportional to critical field strength, to be reduced to a greater extent as compared to a silicon semiconductor and therefore, have gained attention recently as an optimal semiconductor for low loss power devices. Further, similar to silicon semiconductors, silicon carbide semiconductors enable formation of an oxide film (SiO2 film) on a silicon carbide semiconductor substrate (a semiconductor substrate that uses a silicon carbide semiconductor) by thermal oxidation.
Therefore, development of SiC-power metal oxide semiconductor field effect transistors (MOSFETs) that have a low ON resistance and fast switching speed and that use an oxide film formed by thermal oxidation as a gate insulating film is advancing. Nonetheless, when a gate insulating film is formed on a surface of a silicon carbide semiconductor base (semiconductor chip) by thermal oxidation, many defects (interface state) are formed near a junction interface (hereinafter, SiO2/SiC interface) of the gate insulating film and a silicon carbide semiconductor portion, and the interface state density (Dit) becomes high. Therefore, problems arise in that channel mobility decreases, ON resistance increases, and conduction loss increases.
As a method of solving these problems, a method of reducing the interface state density of the SiO2/SiC interface by forming an oxide film on a silicon carbide semiconductor substrate by thermal oxidation in an atmosphere that includes nitrous oxide (N2O) or nitric oxide (NO) has been proposed. The oxide film to become a gate insulating film is formed by thermal oxidation in an atmosphere that includes nitrous oxide or nitric oxide whereby the interface state density of the SiO2/SiC interface may be made to be 2×1012 cm−2 eV−1 or less to realize high channel mobility. Therefore, in a SiC-MOSFET, formation of a metal oxide semiconductor (MOS) gate structure that has a good-quality oxide film as a gate insulating film becomes possible.
A conventional structure of a semiconductor device that uses a silicon carbide semiconductor (hereafter, silicon carbide semiconductor device) will be described taking a SiC-vertical MOSFET of a planar gate structure as an example. FIGS. 8 and 12 are cross-sectional views of a structure of a conventional silicon carbide semiconductor device. In a conventional silicon carbide semiconductor device depicted in FIGS. 8 and 12, on a front surface of an n+-type silicon carbide substrate 101 becoming an n+-type drain region, an n−-type silicon carbide epitaxial layer becoming an n−-type drift layer 102, and a p−-type epitaxial semiconductor layer becoming a p−-type well layer 104 are sequentially deposited. Hereinafter, a stacked base constituted by the n−-type drift layer 102 and the p−-type well layer 104 sequentially stacked on the n+-type silicon carbide substrate 101 is regarded as a silicon carbide semiconductor base.
On a front surface side (the surface on the p−-type well layer 104 side) of the silicon carbide semiconductor base, a MOS gate structure constituted by a p-type semiconductor region 103, a p−-type well layer 104, a p+-type contact region 105, an n+-type source region 106, a gate insulating film 108, and a gate electrode 109 is provided. The p-type semiconductor region 103 and the p−-type well layer 104 function as a base region. An interlayer insulating film 110 is provided so as to cover the gate electrode 109. A front silicide layer 112 forms an ohmic contact (electrical contact portion) with a silicon carbide semiconductor portion in a contact hole that penetrates the interlayer insulating film 110 in a depth direction.
The front silicide layer 112 is, for example, a nickel silicide (NiSi) layer. On the interlayer insulating film 110 and the front silicide layer 112, a source electrode 114 is provided. The source electrode 114 is electrically connected to the p+-type contact region 105 and the n+-type source region 106 by the front silicide layer 112, and is electrically insulated from the gate electrode 109 by the interlayer insulating film 110. As depicted in FIG. 8, a titanium nitride (TiN) film 111 may be provided between the interlayer insulating film 110 and the source electrode 114. The titanium nitride film 111 is electrically insulated from the gate electrode 109 by the interlayer insulating film 110.
A rear surface silicide layer 113 is provided on an entire rear surface of the silicon carbide semiconductor base (a surface on an n+-type silicon carbide substrate 101 side, i.e., a rear surface of the n+-type silicon carbide substrate 101) (not depicted in FIG. 12), and a rear electrode 115 to become a drain electrode is provided on the rear surface silicide layer 113. Reference numeral 107 is an n−-type junction field effect transistor (JFET) region provided at a portion of the n−-type drift layer 102 directly beneath the gate electrode 109 (portion facing the gate electrode 109 via the gate insulating film 108) and between the p−-type well layer 104 and an adjacent p−-type well layer 104. Reference numeral 116 in FIG. 12 is a passivation protective film.
A conventional method of manufacturing a silicon carbide semiconductor device will be described with reference to FIG. 8. First, on the front surface of the n+-type silicon carbide substrate 101 becoming the n+-type drain region, the n−-type drift layer 102 doped with 5×1015/cm3 to 1×1016/cm3 of nitrogen (N) is deposited (formed) by epitaxial growth to have a thickness of 10 μm. Next, the p-type semiconductor region 103 is selectively formed in the surface layer of the n−-type drift layer 102 by ion implantation of a p-type impurity. On the n−-type drift layer 102, the p−-type well layer 104 doped with 5×1015/cm3 of aluminum (Al) is deposited by epitaxial growth so as to cover the p-type semiconductor region 103 and to have a thickness of 0.5 μm.
In the p−-type well layer 104, the JFET region 107 is selectively formed by ion implantation of nitrogen so as to penetrate the p−-type well layer 104 in the depth direction (base-depth direction) and reach the n−-type drift layer 102. Next, in the p−-type well layer 104, the n+-type source region 106 is selectively formed away from the JFET region 107 by ion implantation of phosphorus (P). Further, in the p−-type well layer 104, the p+-type contact region 105 contacting the n+-type source region 106 is selectively formed by ion implantation of aluminum. Next, activation annealing (heat treatment) is performed at a temperature of 1600 degrees C. in an argon (Ar) atmosphere.
Next, on the surface of a portion of the p−-type well layer 104 between the JFET region 107 and the n+-type source region 106, the gate insulating film 108 is formed to have a thickness of 70 nm by thermal oxidation in a nitrous oxide atmosphere. On the gate insulating film 108, poly-silicon (poly-Si) layer becoming the gate electrode 109 is formed. Next, on the entire front surface of the silicon carbide semiconductor base, the interlayer insulating film 110 is formed so as to cover the gate electrode 109. Next, a contact hole penetrating the interlayer insulating film 110 in the depth direction is formed by photolithography and etching to expose the p+-type contact region 105 and the n+-type source region 106 in the contact hole.
Next, on the entire front surface of the silicon carbide semiconductor base, the titanium nitride film 111 is formed so as to cover the interlayer insulating film 110. Next, a portion of the titanium nitride film 111 covering the p+-type contact region 105 and the n+-type source region 106 in the contact hole is removed by photolithography and etching to again expose the p+-type contact region 105 and the n+-type source region 106 in the contact hole. Next, on the silicon carbide semiconductor portion exposed in the contact hole a nickel (Ni) film is formed and on the rear surface of the silicon carbide semiconductor base, a nickel film and a titanium (Ti) film are sequentially deposited (formed).
Next, the front silicide layer 112 and the rear surface silicide layer 113 are respectively formed on the surfaces of the base by sintering (heat treatment). Next, on the interlayer insulating film 110 and the front silicide layer 112, an aluminum layer becoming the source electrode 114 is deposited to have a thickness of 5.0 μm. On the source electrode 114, a polyimide layer to become the non-depicted passivation protective film is formed, and the passivation protective film is hardened (cured) by heat treatment at a temperature of 380 degrees C. Thereafter, on the rear surface silicide layer 113, the rear electrode 115 is formed whereby the SiC-vertical MOSFET depicted in FIG. 8 is completed.
When another SiC-vertical MOSFET depicted in FIG. 12 is formed, after the contact hole is formed, the step of forming the titanium nitride film 111 is omitted and the nickel layer becoming the front silicide layer 112 is formed in the contact hole.
As another SiC-vertical MOSFET, the following device has been proposed. A silicide layer is formed on a source region and a contact region in a DMOSFET region. A metal layer constituting a Schottky electrode is formed on a drift-epi layer and a well region in a SBD region. The metal layer extends from the Schottky electrode and contacts the silicide layer, and is formed from a material selected from a group including titanium, tantalum (Ta), and the nitrides thereof. Further, it has been disclosed that it does not matter even if at least a portion of the metal layer has been removed on interlayer insulating film (for example, refer to Japanese Laid-Open Patent Publication No. 2009-194127 (paragraph 0066, FIG. 1, and Abstract)).
Further, as another SiC-vertical MOSFET, a device has been proposed that includes a poly-silicon gate electrode provided on a semiconductor layer and a source region that is an impurity region formed on the semiconductor layer. The top of the gate electrode is covered by an interlayer insulating film and an aluminum source electrode extends on the interlayer insulating film. An aluminum gate pad is connected to the gate electrode. A barrier metal layer that suppresses the diffusion of aluminum is arranged between the source electrode and the interlayer insulating film; and between the gate pad and the gate electrode. The barrier metal layer is formed from titanium (Ti) or titanium nitride (TiN), or titanium silicon (TiSi) (for example, refer to Japanese Laid-Open Patent Publication No. 2012-129503).